The present invention relates to clock signal regenerators, and more particularly, to ones that work at extremely high speeds.
Recently interest has grown in digital video signal transmission wherein the luminance signal (Y) is 8-bit sampled at 13.5 MHz and the R-Y and B-Y color difference signals are each 8-bit sampled at 6.75 MHz. Serial transmission requires a data rate of 8(13.5+6.75+6.75)=216 Mbits/s. Since the data signal is transmitted asynchronously (without a separate sync or clock signal), the clock signal must be recovered from the data signal itself.
A typical prior art clock regenerator uses a PLL (phase-locked-loop) oscillator which is controlled by the received signal. The oscillator output signal is applied to a variable phase shifter and then to a clock driver, which shifter is adjusted so that the positive going transitions of the phase shifted signal occur in the middle of the received data pulses. A data regenerator receives both the phase-shifted signal from the driver and the data signal and supplies a regenerated data signal. However, at a 216 Mbits/s data rate, the positive going transitions of the clock signal must occur within about .+-.2 ns of the center of the received data bits. With the prior art this accuracy is not achieved due to propagation delays in the PLL and clock driver.
It is therefore desirable to provide a clock regenerator that can be used at high frequencies.